Traveling Speculations: An Integrated Prediction Strategy for Wide-Issue Microprocessors

Performing multiple, accurate, low-latency predictions is crucial to improving instruction throughput in future wide-issue microprocessors. However, demands of wide-issue processing coupled with implementation challenges posed by high clock frequencies present obstacles to these prediction goals. This paper proposes the Traveling Speculation framework to accommodate predictions in a wide-issue environment. Instead of using large centralized data tables to perform predictions, distributed predictors are introduced along with the Traveling Speculation hint, or tint. A tint contains execution history and is assigned to each instruction that is in-flight or in the trace cache. The tint can be related to branch behavior, cache behavior, value prediction, or any history-based aspect of microarchitecture. By associating a unique tint with each instruction in the trace cache, a per-instruction, interference-free execution history is maintained, providing superior prediction accuracy and instruction coverage in a low-latency manner. Our results show that the Traveling Speculation framework improves prediction accuracy and provides personalized execution history to a high percentage of dynamic instructions. Value prediction using Traveling Speculation tints improves instruction throughput by 9.7% over the base model, in comparison to 5.0% obtained by a table-based value predictor. Similarly, speculative memory forwarding using tints improves instruction throughput by 11.8% compared to 7.3% obtained using a memory renaming scheme.